In serial input to parallel output shift registers, a serial bit stream is clocked through a series of serial registers and latched into parallel outputs. The number of parallel bits on the output is dependent on the number of bits shifted serially through the registers before a parallel latch is enabled.
Such a device has certain shortcomings, for example, in a bit stuffing multiplexer circuit. A bit stuffing multiplexer inputs a signal at one frequency and stuffs (adds) bits into that signal, thus outputting a signal at a higher frequency. Such are useful in multiplexing schemes for interleaving signals of different rates. See, for example, American National Standards for Telecommunications, Digital Hierarchy-Optical Interface Rates and Formats Specification, ANSI T1.105-1988. The multiplexer circuit consists of a buffer, a buffer write controller and a buffer read controller. The serial input to parallel output shift register will be located in the write controller and will generate the bit stuffing pattern by outputting gaps in the input signal where stuff data will be located. The read controller will generate the output signal framing pattern by placing additional gaps in the input signal.
The shortcomings of the above mentioned device in the bit stuffing multiplexer example are that (1) the location of the start of the bit stuffing pattern determined by the write controller cannot easily be fixed relative to the framing pattern, and (2) a control signal(s) from the write controller to the read controller must be passed through the buffer. The bit stuffing pattern is generated using a clock on the input side of the buffer, a clock that is asynchronous to the output clock. Therefore, when the circuit is initialized, the bit stuffing pattern will start at random locations relative to the framing pattern of the output signal. The start of the bit stuffing pattern could be fixed relative to the framing pattern if control signals were passed through an additional buffer, but passing control signals through a buffer creates other shortcomings. If the circuit writing the control signals into the buffer fails when a control signal is in the buffer, then the read control circuit will read the control signal at a rate much higher than the bit stuffing pattern rate which will corrupt the framing pattern of the output signal.